The present invention relates generally to semiconductor devices, and more particularly, to multi-bit non-volatile memory semiconductor devices and method therefor.
One type of non-volatile memory uses traps in an insulating layer for charge storage. One material used in such a manner is silicon nitride. Typically, the nitride charge storage layer is surrounded by other insulating layers such as oxide forming an oxide-nitride-oxide (ONO) structure. Charge stored within the nitride is used to manipulate a threshold voltage of the transistor, and in this manner store data. A conventional non-volatile memory gate cell typically exists in one of two states representing either a logical zero or a logical one. To increase the capacity of a memory device without significantly increasing the size of the memory, a multi-bit memory cell may be used that is capable of storing more than two states. Non-volatile memory cells of this type, referred to herein as multi-bit memory cells, have been historically implemented by controlling the amount of charge that is injected into portions of the nitride charge storage layer.
The reliability of multi-bit memory cells that rely on localization of charge is susceptible to charge migration that delocalizes the stored charge. More specifically, the charge may migrate through the nitride layer, causing the stored logic states to change. In multi-bit non-volatile memory cells that use multiple independent floating gates, it has been necessary to use multiple non-self-aligned masking steps to fabricate the multiple floating gates, significantly increasing the cost of the device due to the increased process complexity and larger size of the memory cell.
Therefore, there is a need for a multi-bit non-volatile memory device having good data retention capabilities while also being inexpensive to manufacture.